Question

Assume we have a computer where the clocks per instruction (CPI) is 1.0 when all memory accesses hit in the cache. The only data accesses are loads and stores, and these total take 40% of the instructions. If the miss penalty is 200 clock cycles and the miss rate is 2% for I-Cache and 5% for D-cache, how much faster would the computer be if all instructions were cache hits

Answer 1

Answer:

6.6 times faster considering I-cache

Explanation:

Given data :

CPI  = 1

Data accesses ( loads and stores ) = 40% of instructions

Miss penalty = 200 clock cycles

Miss rate = 2% for I-cache ,  5% for D-cache

Determine how much faster the computer will be if all instructions were Cache hits

In this condition the memory stall = 0

hence: CPU ideal time = ( Ic * CP1  + memory stall ) * clock cycle time --- ( 1 )

                                     = ( Ic * 1 + 0 ) * clock cycle time

Note : Memory stall = Ic * ( 1 + load fraction ) * miss rate * miss penalty  --- ( 2)

back to equation 1

Memory stall ( for I-cache ) = Ic * ( 1 + 40% ) * 2% * 200

                                              = 5.6 Ic

Input value into equation 1

CPU ideal time = Ic * 1 + 5.6Ic * clock cycle time

                         = ( 6.6 Ic ) * clock cycle time

To determine how much faster we take the ratio of the CPU ideal time

=   6.6 Ic * clock cycle time / 1  Ic * clock cycle time

= 6.6 times faster